1. Field of the Invention
The present invention relates to a level shifter circuit, and paticular to a level shifter circuit which is capable of outputting at least three different voltage levels.
2. Background of the Related Art
FIG. 1 illustrates a voltage level translator according to the background art. An inverter INV11 inverts an input signal IN. An NMOS transistor NM11 includes a gate connected for receiving an output signal from the inverter INV11, a source connected to a ground voltage VSS, and a drain connected with a node B. An NMOS transistor NM12 includes a gate connected to receive an externally applied voltage VCC, a source connected to a node B, and a drain connected to a node C. An NMOS transistor NM13 includes a gate connected to receive the externally applied voltage VCC, a source receiving an output signal from the inverter INV11, and a drain connected to a node D. An NMOS transistor NM14 includes a gate receiving a supply voltage VCCp, a source connected to the node D, and the drain connected to the node E. An NMOS transistor NM15 includes a gate receiving the supply voltage VCCp and a source receiving the externally applied voltage.
A PMOS transistor PM11 includes a gate connected to a node E, and a drain connected to the node C, wherein the supply voltage VCCp is supplied to the source and the substrate. A PMOS transistor PM12 includes the gate connected to the node C, and a drain connected to the node E, wherein the supply voltage VCCp is supplied to the source and the substrate, respectively. A PMOS transistor PM13 includes a gate connected to the node C, and a drain connected to a node O, wherein the supply voltage VCCp is supplied to the 5 source and the substrate. A PMOS transistor PM14 includes a gate connected to the node E, a source connected to the drain of the PMOS transistor PM13, and a drain connected to the drain of the NMOS transistor NM15, wherein the supply voltage VCCp is applied to the substrate. An output signal OUT is outputted at the node O.
As shown in FIGS. 2A through 2G, when the input signal IN is triggered from a high level to a low level, the signal transits from the low level to high level at the node A which is an output terminal of the inverter INV11. Therefore, the NMOS transistor NM11 is turned on, and the level of the signal becomes a low level a the node B. Since the NMOS transistor NM12 is always turned on, the level of the signal becomes a low level at the node C.
At the node D, the level of the signal is within a range of VCC-Vt by the NMOS transistor NM13. When the level of the signal becomes a low level at the node C, the PMOS transistor PM12 is activated, such that the signal level at the node E is increased up to the supply voltage VCCp, and the signal level transits to the level of VCCp-Vt, where Vt is a threshold voltage of about 0.7 volts. Therefore, the PMOS transistors PM11 and PM14 are turned off. Since the signal level is a low level at the node C, the PMOS transistor PM13 is turned on, and the signal level at the node O becomes the supply voltage VCCp. Namely, the output signal OUT level becomes the supply voltage VCCp.
Thereafter, when the input signal IN transits from the low level to the high level, the signal level transits from the high level to the low level at the node A. Thereafter, the NMOS transistor NM11 is turned off, and the signal level transits to a low level at the node D. Therefore, the signal level becomes a low level at the node E, and the PMOS transistor PM11 is activated. The signal level at the node C is increased to the supply voltage VCCp, and the PMOS transistors PM12 and PM13 are turned off. Since the signal level is low at the node E, the PMOS transistor PM14 is activated. Further, since the NMOS transistor NM15 is originally turned on, the output signal OUT becomes an externally applied voltage VCC level at the node O.
In order to use the voltage level translator as a transfer gate driver in a memory circuit such as the DRAM, the output signal OUT level is the externally applied voltage VCC or VCCp. However, in the case of the selected block, the output level should be able to transit to the ground voltage VSS. In order to output the ground voltage VSS, additional circuit needs to be provided, which is disadvantageous for reducing the layout area.